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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/El-KadyFHP22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alexander_El-Kady>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Apostolos_P._Fournaris>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Evangelos_Haleplidis>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vassilis_Paliouras>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI-SoC54400.2022.9939657>
foaf:homepage <https://doi.org/10.1109/VLSI-SoC54400.2022.9939657>
dc:identifier DBLP conf/vlsi/El-KadyFHP22 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI-SoC54400.2022.9939657 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label High-Level Synthesis design approach for Number-Theoretic Multiplier. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alexander_El-Kady>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Apostolos_P._Fournaris>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Evangelos_Haleplidis>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vassilis_Paliouras>
swrc:pages 1-6 (xsd:string)
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owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsi/El-KadyFHP22/dblp>
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2022.html#El-KadyFHP22>
rdfs:seeAlso <https://doi.org/10.1109/VLSI-SoC54400.2022.9939657>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsi>
dc:title High-Level Synthesis design approach for Number-Theoretic Multiplier. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document