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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/FariasNBS22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Diego_V._Cirilo_do_Nascimento>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Johannes_W._Farias>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Samuel_Xavier_de_Souza>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tiago_Barros>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI-SoC54400.2022.9939597>
foaf:homepage <https://doi.org/10.1109/VLSI-SoC54400.2022.9939597>
dc:identifier DBLP conf/vlsi/FariasNBS22 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI-SoC54400.2022.9939597 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label Speculative guardband: exploiting critical-delay variations across cached instructions. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Diego_V._Cirilo_do_Nascimento>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Johannes_W._Farias>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Samuel_Xavier_de_Souza>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tiago_Barros>
swrc:pages 1-2 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/2022>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsi/FariasNBS22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsi/FariasNBS22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2022.html#FariasNBS22>
rdfs:seeAlso <https://doi.org/10.1109/VLSI-SoC54400.2022.9939597>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsi>
dc:title Speculative guardband: exploiting critical-delay variations across cached instructions. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document