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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/FolcoBFR05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bertrand_Folco>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Laurent_Fesquet>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marc_Renaudin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vivian_Br%E2%88%9A%C2%A9gier>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-0-387-73661-7%5F5>
foaf:homepage <https://doi.org/10.1007/978-0-387-73661-7_5>
dc:identifier DBLP conf/vlsi/FolcoBFR05 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-0-387-73661-7%5F5 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
rdfs:label Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bertrand_Folco>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Laurent_Fesquet>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marc_Renaudin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vivian_Br%E2%88%9A%C2%A9gier>
swrc:pages 55-69 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/2005soc>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsi/FolcoBFR05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsi/FolcoBFR05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2005.html#FolcoBFR05>
rdfs:seeAlso <https://doi.org/10.1007/978-0-387-73661-7_5>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsi>
dc:title Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document