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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/KhatibACASF15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chadi_Al_Khatib>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chouki_Aktouf>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Claire_Aupetit>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cyril_Chevalier>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gilles_Sicard>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Laurent_Fesquet>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI-SoC.2015.7314435>
foaf:homepage <https://doi.org/10.1109/VLSI-SoC.2015.7314435>
dc:identifier DBLP conf/vlsi/KhatibACASF15 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI-SoC.2015.7314435 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
rdfs:label A generic clock controller for low power systems: Experimentation on an AXI bus. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chadi_Al_Khatib>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chouki_Aktouf>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Claire_Aupetit>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Cyril_Chevalier>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gilles_Sicard>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Laurent_Fesquet>
swrc:pages 307-312 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/2015soc>
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rdfs:seeAlso <https://doi.org/10.1109/VLSI-SoC.2015.7314435>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsi>
dc:title A generic clock controller for low power systems: Experimentation on an AXI bus. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document