MDCT IP Core Generator with Architectural Model Simulation.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/MalikBPS06
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/MalikBPS06
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Marcel_Bal%E2%88%9A%C2%B0z
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Martin_Simlast%E2%88%9A%E2%89%A0k
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Peter_Mal%E2%88%9A%E2%89%A0k
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Tom%E2%88%9A%C2%B0s_Pikula
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FVLSISOC.2006.313286
>
foaf:
homepage
<
https://doi.org/10.1109/VLSISOC.2006.313286
>
dc:
identifier
DBLP conf/vlsi/MalikBPS06
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FVLSISOC.2006.313286
(xsd:string)
dcterms:
issued
2006
(xsd:gYear)
rdfs:
label
MDCT IP Core Generator with Architectural Model Simulation.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Marcel_Bal%E2%88%9A%C2%B0z
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Martin_Simlast%E2%88%9A%E2%89%A0k
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Peter_Mal%E2%88%9A%E2%89%A0k
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Tom%E2%88%9A%C2%B0s_Pikula
>
swrc:
pages
18-23
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/2006soc
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/vlsi/MalikBPS06/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/vlsi/MalikBPS06
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2006.html#MalikBPS06
>
rdfs:
seeAlso
<
https://doi.org/10.1109/VLSISOC.2006.313286
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/vlsi
>
dc:
title
MDCT IP Core Generator with Architectural Model Simulation.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document