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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/MasoumianMWYSHT23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Geert_Jan_Schrijen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Karthik_Keni_Yerriswamy>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mottaqiallah_Taouil>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Roel_Maes>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rui_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Said_Hamdioui>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shayesteh_Masoumian>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI-SoC57769.2023.10321895>
foaf:homepage <https://doi.org/10.1109/VLSI-SoC57769.2023.10321895>
dc:identifier DBLP conf/vlsi/MasoumianMWYSHT23 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI-SoC57769.2023.10321895 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
rdfs:label Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Geert_Jan_Schrijen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Karthik_Keni_Yerriswamy>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mottaqiallah_Taouil>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Roel_Maes>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rui_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Said_Hamdioui>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shayesteh_Masoumian>
swrc:pages 1-6 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/2023>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsi/MasoumianMWYSHT23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsi/MasoumianMWYSHT23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2023.html#MasoumianMWYSHT23>
rdfs:seeAlso <https://doi.org/10.1109/VLSI-SoC57769.2023.10321895>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsi>
dc:title Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document