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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/MiyakoshiMHIIKYM06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hiroshi_Kawaguchi_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Junichi_Miyakoshi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masahiko_Yoshimoto>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masaki_Hamamoto>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Takahiro_Iinuma>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tetsuro_Matsuno>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tomokazu_Ishihara>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yuichiro_Murachi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSISOC.2006.313232>
foaf:homepage <https://doi.org/10.1109/VLSISOC.2006.313232>
dc:identifier DBLP conf/vlsi/MiyakoshiMHIIKYM06 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSISOC.2006.313232 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hiroshi_Kawaguchi_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Junichi_Miyakoshi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masahiko_Yoshimoto>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masaki_Hamamoto>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Takahiro_Iinuma>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tetsuro_Matsuno>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tomokazu_Ishihara>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yuichiro_Murachi>
swrc:pages 192-197 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/2006soc>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsi/MiyakoshiMHIIKYM06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsi/MiyakoshiMHIIKYM06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2006.html#MiyakoshiMHIIKYM06>
rdfs:seeAlso <https://doi.org/10.1109/VLSISOC.2006.313232>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsi>
dc:title A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document