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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/NunnaMYM12>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Farhad_Mehdipour>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kazuaki_J._Murakami>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Krishna_Chaitanya_Nunna>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masayoshi_Yoshimura>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI-SoC.2012.6379032>
foaf:homepage <https://doi.org/10.1109/VLSI-SoC.2012.6379032>
dc:identifier DBLP conf/vlsi/NunnaMYM12 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI-SoC.2012.6379032 (xsd:string)
dcterms:issued 2012 (xsd:gYear)
rdfs:label Methodology for early estimation of hierarchical routing resources in 3D FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Farhad_Mehdipour>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kazuaki_J._Murakami>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Krishna_Chaitanya_Nunna>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masayoshi_Yoshimura>
swrc:pages 213-218 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/2012soc>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsi/NunnaMYM12/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsi/NunnaMYM12>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2012.html#NunnaMYM12>
rdfs:seeAlso <https://doi.org/10.1109/VLSI-SoC.2012.6379032>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsi>
dc:title Methodology for early estimation of hierarchical routing resources in 3D FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document