An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/PerezVC18
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/PerezVC18
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Hector_Villacorta
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/V%E2%88%9A%E2%89%A0ctor_H._Champac
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Zahira_Perez
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FVLSI-SoC.2018.8644864
>
foaf:
homepage
<
https://doi.org/10.1109/VLSI-SoC.2018.8644864
>
dc:
identifier
DBLP conf/vlsi/PerezVC18
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FVLSI-SoC.2018.8644864
(xsd:string)
dcterms:
issued
2018
(xsd:gYear)
rdfs:
label
An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Hector_Villacorta
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/V%E2%88%9A%E2%89%A0ctor_H._Champac
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Zahira_Perez
>
swrc:
pages
77-82
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/2018soc
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/vlsi/PerezVC18/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/vlsi/PerezVC18
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2018.html#PerezVC18
>
rdfs:
seeAlso
<
https://doi.org/10.1109/VLSI-SoC.2018.8644864
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/vlsi
>
dc:
title
An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document