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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/PlassanPMRSB16>
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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fahim_Rahim>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Guillaume_Plassan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hans-J%E2%88%9A%E2%88%82rg_Peter>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Katell_Morin-Allory>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shaker_Sarwary>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI-SoC.2016.7753555>
foaf:homepage <https://doi.org/10.1109/VLSI-SoC.2016.7753555>
dc:identifier DBLP conf/vlsi/PlassanPMRSB16 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI-SoC.2016.7753555 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
rdfs:label Conclusively verifying clock-domain crossings in very large hardware designs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dominique_Borrione>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fahim_Rahim>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Guillaume_Plassan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hans-J%E2%88%9A%E2%88%82rg_Peter>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Katell_Morin-Allory>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shaker_Sarwary>
swrc:pages 1-6 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1109/VLSI-SoC.2016.7753555>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsi>
dc:title Conclusively verifying clock-domain crossings in very large hardware designs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document