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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/PoittevinMOMLDB20>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Abhishek_Kumar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arnaud_Poittevin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Aur%E2%88%9A%C2%A9lie_Lecestre>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C%E2%88%9A%C2%A9dric_Marchand_0002>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chhandak_Mukherjee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cristell_Maneux>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fran%E2%88%9A%C3%9Fois_Marc>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Guilhem_Larrieu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ian_O%27Connor>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marina_Deng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/S%E2%88%9A%C2%A9bastien_Le_Beux>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-030-81641-4%5F14>
foaf:homepage <https://doi.org/10.1007/978-3-030-81641-4_14>
dc:identifier DBLP conf/vlsi/PoittevinMOMLDB20 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-030-81641-4%5F14 (xsd:string)
dcterms:issued 2020 (xsd:gYear)
rdfs:label 3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Abhishek_Kumar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arnaud_Poittevin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Aur%E2%88%9A%C2%A9lie_Lecestre>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C%E2%88%9A%C2%A9dric_Marchand_0002>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chhandak_Mukherjee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Cristell_Maneux>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fran%E2%88%9A%C3%9Fois_Marc>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Guilhem_Larrieu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ian_O%27Connor>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marina_Deng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/S%E2%88%9A%C2%A9bastien_Le_Beux>
swrc:pages 301-321 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/2020socs>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsi/PoittevinMOMLDB20/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsi/PoittevinMOMLDB20>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2020s.html#PoittevinMOMLDB20>
rdfs:seeAlso <https://doi.org/10.1007/978-3-030-81641-4_14>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsi>
dc:title 3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document