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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/ReveilMMDMKLLPO22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Abhishek_Kumar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arnaud_Poittevin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Aur%E2%88%9A%C2%A9lie_Lecestre>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chhandak_Mukherjee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cristell_Maneux>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_Pirker>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fran%E2%88%9A%C3%9Fois_Marc>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Guilhem_Larrieu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ian_O%27Connor>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lucas_R%E2%88%9A%C2%A9veil>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marina_Deng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Oskar_Baumgartner>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI-SoC54400.2022.9939576>
foaf:homepage <https://doi.org/10.1109/VLSI-SoC54400.2022.9939576>
dc:identifier DBLP conf/vlsi/ReveilMMDMKLLPO22 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI-SoC54400.2022.9939576 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Abhishek_Kumar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arnaud_Poittevin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Aur%E2%88%9A%C2%A9lie_Lecestre>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chhandak_Mukherjee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Cristell_Maneux>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_Pirker>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fran%E2%88%9A%C3%9Fois_Marc>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Guilhem_Larrieu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ian_O%27Connor>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lucas_R%E2%88%9A%C2%A9veil>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marina_Deng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Oskar_Baumgartner>
swrc:pages 1-2 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/2022>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsi/ReveilMMDMKLLPO22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsi/ReveilMMDMKLLPO22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2022.html#ReveilMMDMKLLPO22>
rdfs:seeAlso <https://doi.org/10.1109/VLSI-SoC54400.2022.9939576>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsi>
dc:title Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document