A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/RoviniGRF07
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/RoviniGRF07
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Francesco_Rossi
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Giuseppe_Gentile
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Luca_Fanucci
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Massimo_Rovini
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FVLSISOC.2007.4402504
>
foaf:
homepage
<
https://doi.org/10.1109/VLSISOC.2007.4402504
>
dc:
identifier
DBLP conf/vlsi/RoviniGRF07
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FVLSISOC.2007.4402504
(xsd:string)
dcterms:
issued
2007
(xsd:gYear)
rdfs:
label
A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Francesco_Rossi
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Giuseppe_Gentile
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Luca_Fanucci
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Massimo_Rovini
>
swrc:
pages
236-241
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/2007soc
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/vlsi/RoviniGRF07/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/vlsi/RoviniGRF07
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2007.html#RoviniGRF07
>
rdfs:
seeAlso
<
https://doi.org/10.1109/VLSISOC.2007.4402504
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/vlsi
>
dc:
title
A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document