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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/SeokPCK14>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Daejin_Park>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Geun_Rae_Cho>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Moon_Gi_Seok>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tag_Gon_Kim>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI-SoC.2014.7004185>
foaf:homepage <https://doi.org/10.1109/VLSI-SoC.2014.7004185>
dc:identifier DBLP conf/vlsi/SeokPCK14 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI-SoC.2014.7004185 (xsd:string)
dcterms:issued 2014 (xsd:gYear)
rdfs:label Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Daejin_Park>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Geun_Rae_Cho>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Moon_Gi_Seok>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tag_Gon_Kim>
swrc:pages 1-6 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/2014soc>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsi/SeokPCK14/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsi/SeokPCK14>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2014.html#SeokPCK14>
rdfs:seeAlso <https://doi.org/10.1109/VLSI-SoC.2014.7004185>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsi>
dc:title Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document