VLSI-Architecture of Radix-2/4/8 SISO Decoder for Turbo Decoding at Multiple Data-rates.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/ShresthaS18
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VLSI-Architecture of Radix-2/4/8 SISO Decoder for Turbo Decoding at Multiple Data-rates.
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