An Area-Efficient Timing Closure Technique for FPGAs Using Shannon's Expansion. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:issued	2003 (xsd:gYear)
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swrc:pages	41-50 (xsd:string)
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dc:title	An Area-Efficient Timing Closure Technique for FPGAs Using Shannon's Expansion. (xsd:string)
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