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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/SundaresanRV07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ranga_Vemuri>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Srividhya_Rammohan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vijay_Sundaresan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSISOC.2007.4402463>
foaf:homepage <https://doi.org/10.1109/VLSISOC.2007.4402463>
dc:identifier DBLP conf/vlsi/SundaresanRV07 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSISOC.2007.4402463 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label Power invariant secure IC design methodology using reduced complementary dynamic and differential logic. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ranga_Vemuri>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Srividhya_Rammohan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vijay_Sundaresan>
swrc:pages 1-6 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/2007soc>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsi/SundaresanRV07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsi/SundaresanRV07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2007.html#SundaresanRV07>
rdfs:seeAlso <https://doi.org/10.1109/VLSISOC.2007.4402463>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsi>
dc:title Power invariant secure IC design methodology using reduced complementary dynamic and differential logic. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document