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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsi/TenaceCMP16a>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andrea_Calimera>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Enrico_Macii>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Massimo_Poncino>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Valerio_Tenace>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-319-67104-8%5F4>
foaf:homepage <https://doi.org/10.1007/978-3-319-67104-8_4>
dc:identifier DBLP conf/vlsi/TenaceCMP16a (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-319-67104-8%5F4 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
rdfs:label Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andrea_Calimera>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Enrico_Macii>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Massimo_Poncino>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Valerio_Tenace>
swrc:pages 60-82 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsi/2016socs>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsi/TenaceCMP16a/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsi/TenaceCMP16a>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2016s.html#TenaceCMP16a>
rdfs:seeAlso <https://doi.org/10.1007/978-3-319-67104-8_4>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsi>
dc:title Logic Synthesis for Silicon and Beyond-Silicon Multi-gate Pass-Logic Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document