A 0.9um2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsic/ChenKDBZ16
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/vlsic/ChenKDBZ16
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Kevin_Zhang_0001
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Sarvesh_H._Kulkarni
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Uddalak_Bhattacharya
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Vincent_E._Dorgan
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Zhanping_Chen
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FVLSIC.2016.7573506
>
foaf:
homepage
<
https://doi.org/10.1109/VLSIC.2016.7573506
>
dc:
identifier
DBLP conf/vlsic/ChenKDBZ16
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FVLSIC.2016.7573506
(xsd:string)
dcterms:
issued
2016
(xsd:gYear)
rdfs:
label
A 0.9um2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Kevin_Zhang_0001
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Sarvesh_H._Kulkarni
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Uddalak_Bhattacharya
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Vincent_E._Dorgan
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Zhanping_Chen
>
swrc:
pages
1-2
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/vlsic/2016
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/vlsic/ChenKDBZ16/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/vlsic/ChenKDBZ16
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#ChenKDBZ16
>
rdfs:
seeAlso
<
https://doi.org/10.1109/VLSIC.2016.7573506
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/vlsic
>
dc:
title
A 0.9um2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document