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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsic/Cho0LZ21>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chester_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sung-Gun_Cho>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei_Tang_0010>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhengya_Zhang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.23919%2FVLSICircuits52068.2021.9492517>
foaf:homepage <https://doi.org/10.23919/VLSICircuits52068.2021.9492517>
dc:identifier DBLP conf/vlsic/Cho0LZ21 (xsd:string)
dc:identifier DOI doi.org%2F10.23919%2FVLSICircuits52068.2021.9492517 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
rdfs:label PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chester_Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sung-Gun_Cho>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei_Tang_0010>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhengya_Zhang>
swrc:pages 1-2 (xsd:string)
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rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsic/vlsic2021.html#Cho0LZ21>
rdfs:seeAlso <https://doi.org/10.23919/VLSICircuits52068.2021.9492517>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsic>
dc:title PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document