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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsic/FerrissPNRPBYSV12>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alberto_Valdes-Garcia>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alexander_V._Rylyakov>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arun_Natarajan_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Aydin_Babakhani>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Benjamin_D._Parker>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bodhisatwa_Sadhu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Daniel_J._Friedman>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jean-Olivier_Plouchart>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_A._Tierno>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mark_A._Ferriss>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Soner_Yaldiz>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSIC.2012.6243847>
foaf:homepage <https://doi.org/10.1109/VLSIC.2012.6243847>
dc:identifier DBLP conf/vlsic/FerrissPNRPBYSV12 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSIC.2012.6243847 (xsd:string)
dcterms:issued 2012 (xsd:gYear)
rdfs:label An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alberto_Valdes-Garcia>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alexander_V._Rylyakov>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arun_Natarajan_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Aydin_Babakhani>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Benjamin_D._Parker>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bodhisatwa_Sadhu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Daniel_J._Friedman>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jean-Olivier_Plouchart>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_A._Tierno>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mark_A._Ferriss>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Soner_Yaldiz>
swrc:pages 176-177 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsic/2012>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsic/FerrissPNRPBYSV12/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsic/FerrissPNRPBYSV12>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsic/vlsic2012.html#FerrissPNRPBYSV12>
rdfs:seeAlso <https://doi.org/10.1109/VLSIC.2012.6243847>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsic>
dc:title An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document