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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsic/LeeVTV21>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hossein_Valavi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jinseok_Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Naveen_Verma>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yinqi_Tang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.23919%2FVLSICircuits52068.2021.9492444>
foaf:homepage <https://doi.org/10.23919/VLSICircuits52068.2021.9492444>
dc:identifier DBLP conf/vlsic/LeeVTV21 (xsd:string)
dc:identifier DOI doi.org%2F10.23919%2FVLSICircuits52068.2021.9492444 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
rdfs:label Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hossein_Valavi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jinseok_Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Naveen_Verma>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yinqi_Tang>
swrc:pages 1-2 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsic/2021>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsic/LeeVTV21/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsic/LeeVTV21>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsic/vlsic2021.html#LeeVTV21>
rdfs:seeAlso <https://doi.org/10.23919/VLSICircuits52068.2021.9492444>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsic>
dc:title Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document