Design and demonstration of reliability-aware Ge gate stacks with 0.5 nm EOT.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsic/LuLNT15
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Design and demonstration of reliability-aware Ge gate stacks with 0.5 nm EOT.
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Design and demonstration of reliability-aware Ge gate stacks with 0.5 nm EOT.
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