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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsic/LuSCRHCCCC21>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bor-Doou_Rong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cheng-Nan_Chang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chia-Wei_Chang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chun_Shiah>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ho-Yin_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Juang-Ying_Chueh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nicky_Lu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tzung-Shen_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei-Jr_Huang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.23919%2FVLSICircuits52068.2021.9492418>
foaf:homepage <https://doi.org/10.23919/VLSICircuits52068.2021.9492418>
dc:identifier DBLP conf/vlsic/LuSCRHCCCC21 (xsd:string)
dc:identifier DOI doi.org%2F10.23919%2FVLSICircuits52068.2021.9492418 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
rdfs:label Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125¬įC and Random Row/Column Access Times Accelerated by 1.5ns. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bor-Doou_Rong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Cheng-Nan_Chang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chia-Wei_Chang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chun_Shiah>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ho-Yin_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Juang-Ying_Chueh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nicky_Lu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tzung-Shen_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei-Jr_Huang>
swrc:pages 1-2 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsic/2021>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsic/LuSCRHCCCC21/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsic/LuSCRHCCCC21>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsic/vlsic2021.html#LuSCRHCCCC21>
rdfs:seeAlso <https://doi.org/10.23919/VLSICircuits52068.2021.9492418>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsic>
dc:title Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125¬įC and Random Row/Column Access Times Accelerated by 1.5ns. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document