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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsic/LuoCSWSLLLLLCSK15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bor-Doou_Rong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cheng-Wen_Wu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chi-Kang_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chia-Hsin_Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chun-Nan_Lu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chun_Shiah>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chung-Hu_Ke>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ding-Ming_Kwai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hsiu-Chuan_Shih>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kuo-Hua_Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mei-Chiang_Lung>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ming-Wei_Li>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nicky_Lu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Patrick_Stolt>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pei-Wen_Luo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Po-Lin_Shih>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shigeki_Tomishima>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shih-Lien_Lu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei_Wu_0024>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yu-Hui_Sung>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yung-Fa_Chou>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSIC.2015.7231256>
foaf:homepage <https://doi.org/10.1109/VLSIC.2015.7231256>
dc:identifier DBLP conf/vlsic/LuoCSWSLLLLLCSK15 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSIC.2015.7231256 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
rdfs:label A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bor-Doou_Rong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Cheng-Wen_Wu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chi-Kang_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chia-Hsin_Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chun-Nan_Lu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chun_Shiah>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chung-Hu_Ke>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ding-Ming_Kwai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hsiu-Chuan_Shih>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kuo-Hua_Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mei-Chiang_Lung>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ming-Wei_Li>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nicky_Lu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Patrick_Stolt>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pei-Wen_Luo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Po-Lin_Shih>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shigeki_Tomishima>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shih-Lien_Lu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei_Wu_0024>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yu-Hui_Sung>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yung-Fa_Chou>
swrc:pages 186- (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsic/2015>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsic/LuoCSWSLLLLLCSK15/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsic/LuoCSWSLLLLLCSK15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsic/vlsic2015.html#LuoCSWSLLLLLCSK15>
rdfs:seeAlso <https://doi.org/10.1109/VLSIC.2015.7231256>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsic>
dc:title A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document