A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/vlsic/RovinskiZAGXTDA19
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Anuj_Rao
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Aporva_Amarnath
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Austin_Rovinski
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Bandhav_Veluri
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Christopher_Batten
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Christopher_Torng
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Chun_Zhao
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Dustin_Richmond
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ian_Galton
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Julian_Puscar
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Khalid_Al-Hawaj
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Luis_Vega
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Michael_B._Taylor
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Paul_Gao_0001
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ritchie_Zhao
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ronald_G._Dreslinski
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Scott_Davidson_0004
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Shaolin_Xie
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Steve_Dai
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Tutu_Ajayi
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Zhiru_Zhang
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.23919%2FVLSIC.2019.8778031
>
foaf:
homepage
<
https://doi.org/10.23919/VLSIC.2019.8778031
>
dc:
identifier
DBLP conf/vlsic/RovinskiZAGXTDA19
(xsd:string)
dc:
identifier
DOI doi.org%2F10.23919%2FVLSIC.2019.8778031
(xsd:string)
dcterms:
issued
2019
(xsd:gYear)
rdfs:
label
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Anuj_Rao
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Aporva_Amarnath
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Austin_Rovinski
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Bandhav_Veluri
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Christopher_Batten
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Christopher_Torng
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Chun_Zhao
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Dustin_Richmond
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ian_Galton
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Julian_Puscar
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Khalid_Al-Hawaj
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Luis_Vega
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Michael_B._Taylor
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Paul_Gao_0001
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ritchie_Zhao
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ronald_G._Dreslinski
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Scott_Davidson_0004
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Shaolin_Xie
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Steve_Dai
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Tutu_Ajayi
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Zhiru_Zhang
>
swrc:
pages
30-
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/vlsic/2019
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/vlsic/RovinskiZAGXTDA19/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/vlsic/RovinskiZAGXTDA19
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/vlsic/vlsic2019.html#RovinskiZAGXTDA19
>
rdfs:
seeAlso
<
https://doi.org/10.23919/VLSIC.2019.8778031
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/vlsic
>
dc:
title
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document