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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsic/ViraraghavanLJC16>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alberto_Cestero>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Balaji_Jayaraman>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dan_Moy>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Derek_Leu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Faraz_Khan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Janakiraman_Viraraghavan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/John_Golz>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ming_Yin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rajesh_Reddy_Tummuru>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ramesh_Raghavan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Robert_Kilker>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Subramanian_S._Iyer>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Thejas_Kempanna>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Toshiaki_Kirihata>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSIC.2016.7573462>
foaf:homepage <https://doi.org/10.1109/VLSIC.2016.7573462>
dc:identifier DBLP conf/vlsic/ViraraghavanLJC16 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSIC.2016.7573462 (xsd:string)
dcterms:issued 2016 (xsd:gYear)
rdfs:label 80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alberto_Cestero>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Balaji_Jayaraman>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dan_Moy>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Derek_Leu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Faraz_Khan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Janakiraman_Viraraghavan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/John_Golz>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ming_Yin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rajesh_Reddy_Tummuru>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ramesh_Raghavan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Robert_Kilker>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Subramanian_S._Iyer>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Thejas_Kempanna>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Toshiaki_Kirihata>
swrc:pages 1-2 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsic/2016>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsic/ViraraghavanLJC16/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsic/ViraraghavanLJC16>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsic/vlsic2016.html#ViraraghavanLJC16>
rdfs:seeAlso <https://doi.org/10.1109/VLSIC.2016.7573462>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsic>
dc:title 80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document