Low-Power Design by Hazard Filtering. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Vishwani_D._Agrawal>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FICVD.1997.568075>
foaf:homepage	<https://doi.org/10.1109/ICVD.1997.568075>
dc:identifier	DBLP conf/vlsid/Agrawal97 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FICVD.1997.568075 (xsd:string)
dcterms:issued	1997 (xsd:gYear)
rdfs:label	Low-Power Design by Hazard Filtering. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Vishwani_D._Agrawal>
swrc:pages	193-197 (xsd:string)
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rdfs:seeAlso	<https://doi.org/10.1109/ICVD.1997.568075>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject	CMOS logic circuits, low-power design, hazard filtering, CMOS circuit, multiple transitions, power consumption, hazard pulses, logic gate, gate delays, differential delay (xsd:string)
dc:title	Low-Power Design by Hazard Filtering. (xsd:string)
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