Multi-way partitioning of VLSI circuits. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Prathima_Agrawal>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FICVD.1996.489641>
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dcterms:issued	1996 (xsd:gYear)
rdfs:label	Multi-way partitioning of VLSI circuits. (xsd:string)
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swrc:pages	393-399 (xsd:string)
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dc:subject	logic partitioning; logic CAD; integrated circuit layout; VLSI; economics; integrated circuit manufacture; delays; minimisation of switching nets; multi-way partitioning; VLSI circuits; hierarchical design processes; cost metric; VLSI layout; average delay; nets cut metric (xsd:string)
dc:title	Multi-way partitioning of VLSI circuits. (xsd:string)
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