[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/AhujaZLS10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Avinash_Lakshminarayana>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sandeep_K._Shukla>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sumit_Ahuja>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei_Zhang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI.Design.2010.58>
foaf:homepage <https://doi.org/10.1109/VLSI.Design.2010.58>
dc:identifier DBLP conf/vlsid/AhujaZLS10 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI.Design.2010.58 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Avinash_Lakshminarayana>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sandeep_K._Shukla>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sumit_Ahuja>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei_Zhang>
swrc:pages 282-287 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/AhujaZLS10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/AhujaZLS10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#AhujaZLS10>
rdfs:seeAlso <https://doi.org/10.1109/VLSI.Design.2010.58>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject High Level Synthesis, Clock-gating, Power Reduction, C2R, Hardware Coprocessor, Software Algorithms (xsd:string)
dc:title A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document