A 16-bit x 16-bit 1.2 őľ CMOS multiplier with low latency vector merging.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/AmendolaSP95
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1995
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A 16-bit x 16-bit 1.2 őľ CMOS multiplier with low latency vector merging.
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multiplying circuits; pipeline arithmetic; VLSI; parallel architectures; data conversion; CMOS logic circuits; CMOS multiplier; low latency vector merging; VLSI architecture; bit-level pipelined architecture; two's-complement binary array multiplier; multiplier architecture; signed-digit radix 2 adders; carry free adders; multiplication; fast conversion scheme; pipelining registers; half adders; positive edge triggered registers; single phase clocking scheme; 16 bit; 1.2 micron; 50 MHz; 3 V
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A 16-bit x 16-bit 1.2 őľ CMOS multiplier with low latency vector merging.
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