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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/AsciaC95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Giuseppe_Ascia>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vincenzo_Catania>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1995.512131>
foaf:homepage <https://doi.org/10.1109/ICVD.1995.512131>
dc:identifier DBLP conf/vlsid/AsciaC95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1995.512131 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Design of a VLSI parallel processor for fuzzy computing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Giuseppe_Ascia>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vincenzo_Catania>
swrc:pages 315-320 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/AsciaC95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/AsciaC95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#AsciaC95>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1995.512131>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject VLSI; parallel architectures; fuzzy logic; inference mechanisms; fuzzy set theory; integrated circuit design; microprocessor chips; VLSI parallel processor; fuzzy computing; fuzzy inferences; /spl alpha/-level sets theory; memory resources; membership functions; parallelism; scalability; processing units; clock frequency; 50 MHz; 8 bit (xsd:string)
dc:title Design of a VLSI parallel processor for fuzzy computing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document