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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/Aziz95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/S._M._Aziz>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1995.512124>
foaf:homepage <https://doi.org/10.1109/ICVD.1995.512124>
dc:identifier DBLP conf/vlsid/Aziz95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1995.512124 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label A C-testable modified Booth's array multiplier. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/S._M._Aziz>
swrc:pages 278-282 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/Aziz95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/Aziz95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#Aziz95>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1995.512124>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject multiplying circuits; digital arithmetic; parallel processing; logic arrays; integrated circuit testing; logic testing; CMOS logic circuits; C-testable multiplier; array multiplier; parallel multiplier; modified Booth algorithm; gate-level design; stuck-at faults (xsd:string)
dc:title A C-testable modified Booth's array multiplier. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document