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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/BabuICC04>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ahsan_Raja_Chowdhury>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hafiz_Md._Hasan_Babu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Md._Rafiqul_Islam_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Syed_Mostahed_Ali_Chowdhury>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.2004.1261020>
foaf:homepage <https://doi.org/10.1109/ICVD.2004.1261020>
dc:identifier DBLP conf/vlsid/BabuICC04 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.2004.1261020 (xsd:string)
dcterms:issued 2004 (xsd:gYear)
rdfs:label Synthesis of Full-Adder Circuit Using Reversible Logic. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ahsan_Raja_Chowdhury>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hafiz_Md._Hasan_Babu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Md._Rafiqul_Islam_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Syed_Mostahed_Ali_Chowdhury>
swrc:pages 757-760 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2004>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/BabuICC04/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/BabuICC04>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2004.html#BabuICC04>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.2004.1261020>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:title Synthesis of Full-Adder Circuit Using Reversible Logic. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document