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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/BagchiD94>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sajal_K._Das_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tanuj_Bagchi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1994.282686>
foaf:homepage <https://doi.org/10.1109/ICVD.1994.282686>
dc:identifier DBLP conf/vlsid/BagchiD94 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1994.282686 (xsd:string)
dcterms:issued 1994 (xsd:gYear)
rdfs:label An Efficient Hybrid Heuristic for the Gate Matrix Layout Problem in VLSI Design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sajal_K._Das_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tanuj_Bagchi>
swrc:pages 207-210 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1994>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/BagchiD94/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/BagchiD94>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1994.html#BagchiD94>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1994.282686>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:title An Efficient Hybrid Heuristic for the Gate Matrix Layout Problem in VLSI Design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document