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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/BalajiCT08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Balaji_Srinivasan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Menka_Tewani>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vinay_Bhaskar_Chandratre>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI.2008.95>
foaf:homepage <https://doi.org/10.1109/VLSI.2008.95>
dc:identifier DBLP conf/vlsid/BalajiCT08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI.2008.95 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label 0.35¬Ķ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Balaji_Srinivasan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Menka_Tewani>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vinay_Bhaskar_Chandratre>
swrc:pages 613-619 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/BalajiCT08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/BalajiCT08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2008.html#BalajiCT08>
rdfs:seeAlso <https://doi.org/10.1109/VLSI.2008.95>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:title 0.35¬Ķ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document