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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/BalakrishnanC96a>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arun_Balakrishnan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Srimat_T._Chakradhar>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1996.489614>
foaf:homepage <https://doi.org/10.1109/ICVD.1996.489614>
dc:identifier DBLP conf/vlsid/BalakrishnanC96a (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1996.489614 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Retiming with logic duplication transformation: theory and an application to partial scan. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arun_Balakrishnan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Srimat_T._Chakradhar>
swrc:pages 296-302 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/BalakrishnanC96a/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/BalakrishnanC96a>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1996.html#BalakrishnanC96a>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1996.489614>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject logic CAD; flip-flops; timing; integer programming; linear programming; circuit CAD; integrated logic circuits; integrated circuit design; sequential circuits; logic design; retiming; logic duplication transformation; partial scan application; RLD configurations; RLD transformation; integer linear program; objective function; testability metrics; polynomial time algorithm; scan flip-flops; sequential circuit design (xsd:string)
dc:title Retiming with logic duplication transformation: theory and an application to partial scan. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document