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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/BaratJBD02>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Francisco_Barat>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Geert_Deconinck>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Murali_Jayapala>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pieter_Op_de_Beeck>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASPDAC.2002.994945>
foaf:homepage <https://doi.org/10.1109/ASPDAC.2002.994945>
dc:identifier DBLP conf/vlsid/BaratJBD02 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASPDAC.2002.994945 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
rdfs:label Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Francisco_Barat>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Geert_Deconinck>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Murali_Jayapala>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pieter_Op_de_Beeck>
swrc:pages 338-344 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2002>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/BaratJBD02/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/BaratJBD02>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2002.html#BaratJBD02>
rdfs:seeAlso <https://doi.org/10.1109/ASPDAC.2002.994945>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject reconfigurable processor, code generation, coarse grained logic, software pipelining, vliw, spatial computation (xsd:string)
dc:title Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document