A VLSI architecture for cellular automata based parallel data compression.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/BhattacharjeeBRSC96
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1996
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A VLSI architecture for cellular automata based parallel data compression.
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VLSI; cellular automata; data compression; parallel architectures; VLSI architecture; cellular automata; parallel data compression; state transition; nongroup CA
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A VLSI architecture for cellular automata based parallel data compression.
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