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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/BradleyV95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ranga_Vemuri>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/William_L._Bradley>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1995.512117>
foaf:homepage <https://doi.org/10.1109/ICVD.1995.512117>
dc:identifier DBLP conf/vlsid/BradleyV95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1995.512117 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Transformations for functional verification of synthesized designs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ranga_Vemuri>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/William_L._Bradley>
swrc:pages 243-248 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/BradleyV95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/BradleyV95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#BradleyV95>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1995.512117>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject logic CAD; transforms; formal verification; clocks; low-level functional verification; synthesized designs; hierarchical system; reachable states; clocking mechanisms; transforms; provably equivalent model; algorithm; hierarchical network of modules; reduced state set; de-phase transform; align transform (xsd:string)
dc:title Transformations for functional verification of synthesized designs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document