Optimum retiming of large sequential circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/Chakradhar95
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/Chakradhar95
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Srimat_T._Chakradhar
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FICVD.1995.512092
>
foaf:
homepage
<
https://doi.org/10.1109/ICVD.1995.512092
>
dc:
identifier
DBLP conf/vlsid/Chakradhar95
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FICVD.1995.512092
(xsd:string)
dcterms:
issued
1995
(xsd:gYear)
rdfs:
label
Optimum retiming of large sequential circuits.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Srimat_T._Chakradhar
>
swrc:
pages
135-140
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1995
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/vlsid/Chakradhar95/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/vlsid/Chakradhar95
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#Chakradhar95
>
rdfs:
seeAlso
<
https://doi.org/10.1109/ICVD.1995.512092
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/vlsid
>
dc:
subject
sequential circuits; linear programming; integer programming; timing; integrated logic circuits; circuit optimisation; delays; logic CAD; circuit CAD; VLSI; optimum retiming; large sequential circuits; fast algorithm; unit delay model; optimum clock period; path graph; flip-flops; integer linear program; linear program relaxation; VLSI circuits
(xsd:string)
dc:
title
Optimum retiming of large sequential circuits.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document