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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/ChanGG10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Puneet_Gupta_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rani_S._Ghaida>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tuck-Boon_Chan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI.Design.2010.24>
foaf:homepage <https://doi.org/10.1109/VLSI.Design.2010.24>
dc:identifier DBLP conf/vlsid/ChanGG10 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI.Design.2010.24 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label Electrical Modeling of Lithographic Imperfections. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Puneet_Gupta_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rani_S._Ghaida>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tuck-Boon_Chan>
swrc:pages 423-428 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/ChanGG10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/ChanGG10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#ChanGG10>
rdfs:seeAlso <https://doi.org/10.1109/VLSI.Design.2010.24>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject lithographic imperfections, non-rectangular, transistor, mosfet (xsd:string)
dc:title Electrical Modeling of Lithographic Imperfections. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document