Ultra low power digital signal processing. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/Chandrakasan96>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Anantha_P._Chandrakasan>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FICVD.1996.489634>
foaf:homepage	<https://doi.org/10.1109/ICVD.1996.489634>
dc:identifier	DBLP conf/vlsid/Chandrakasan96 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FICVD.1996.489634 (xsd:string)
dcterms:issued	1996 (xsd:gYear)
rdfs:label	Ultra low power digital signal processing. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Anantha_P._Chandrakasan>
swrc:pages	352-357 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1996>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/vlsid/Chandrakasan96/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/vlsid/Chandrakasan96>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/vlsid/vlsid1996.html#Chandrakasan96>
rdfs:seeAlso	<https://doi.org/10.1109/ICVD.1996.489634>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject	digital signal processing chips; integrated circuit design; circuit optimisation; ultra low power digital signal processing; portable wireless device; DSP; power consumption; capacitance minimization; data representation; spatial signal correlations; temporal signal correlations; re-synchronization; glitching; logic design; circuit design; voltage scaling; circuit optimization; architecture optimization; switching; operation reduction; 1 V (xsd:string)
dc:title	Ultra low power digital signal processing. (xsd:string)
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