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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/ChandyB96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/John_A._Chandy>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Prithviraj_Banerjee>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1996.489451>
foaf:homepage <https://doi.org/10.1109/ICVD.1996.489451>
dc:identifier DBLP conf/vlsid/ChandyB96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1996.489451 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Parallel simulated annealing strategies for VLSI cell placement. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/John_A._Chandy>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Prithviraj_Banerjee>
swrc:pages 37-42 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/ChandyB96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/ChandyB96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1996.html#ChandyB96>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1996.489451>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject VLSI; integrated circuit layout; circuit layout CAD; simulated annealing; parallel algorithms; Markov processes; parallel simulated annealing strategies; VLSI cell placement; standard cell placement; VLSI design; cell placement annealing; multiple Markov chains; speculative computation; parallel moves approach (xsd:string)
dc:title Parallel simulated annealing strategies for VLSI cell placement. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document