An improved output compaction technique for built-in self-test in VLSI circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/DasHJN95
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1995
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An improved output compaction technique for built-in self-test in VLSI circuits.
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VLSI; integrated circuit testing; combinational circuits; logic testing; integrated logic circuits; design for testability; automatic testing; probability; Boolean functions; built-in self test; digital integrated circuits; output compaction technique; built-in self-test; VLSI circuits; space compression technique; digital circuits; compaction tree generation; detectable error probability; Boolean difference method; syndrome counter; combinational circuits; fault coverage; BIST; DFT
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An improved output compaction technique for built-in self-test in VLSI circuits.
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