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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/DasasathyanRV02>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rajesh_Radhakrishnan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ranga_Vemuri>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Srinivasan_Dasasathyan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FASPDAC.2002.994943>
foaf:homepage <https://doi.org/10.1109/ASPDAC.2002.994943>
dc:identifier DBLP conf/vlsid/DasasathyanRV02 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FASPDAC.2002.994943 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
rdfs:label Framework for Synthesis of Virtual Pipelines. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rajesh_Radhakrishnan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ranga_Vemuri>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Srinivasan_Dasasathyan>
swrc:pages 326-331 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2002>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/DasasathyanRV02/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/DasasathyanRV02>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2002.html#DasasathyanRV02>
rdfs:seeAlso <https://doi.org/10.1109/ASPDAC.2002.994943>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject Partial Reconfiguration, Dynamic Reconfiguration, Virtual Pipeline, SLAAC-1V board, JHDL, Pipelining, FPGAs (xsd:string)
dc:title Framework for Synthesis of Virtual Pipelines. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document