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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/DasguptaSB95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bhargab_B._Bhattacharya>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/P._S._Dasgupta>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Susmita_Sur-Kolay>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1995.512141>
foaf:homepage <https://doi.org/10.1109/ICVD.1995.512141>
dc:identifier DBLP conf/vlsid/DasguptaSB95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1995.512141 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label VLSI floorplan generation and area optimization using AND-OR graph search. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bhargab_B._Bhattacharya>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/P._S._Dasgupta>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Susmita_Sur-Kolay>
swrc:pages 370-375 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/DasguptaSB95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/DasguptaSB95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#DasguptaSB95>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1995.512141>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject VLSI; circuit layout CAD; circuit optimisation; integrated circuit interconnections; graph theory; VLSI floorplan generation; area optimization; AND-OR graph search; rectangular dualization; adjacency graph; aspect ratios; minimum-area floorplan; optimal sizing; heuristic search method; top-down first phase; search effort; bottom-up polynomial-time algorithm; nonslicible floorplans (xsd:string)
dc:title VLSI floorplan generation and area optimization using AND-OR graph search. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document