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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/DevganR95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anirudh_Devgan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ronald_A._Rohrer>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1995.512114>
foaf:homepage <https://doi.org/10.1109/ICVD.1995.512114>
dc:identifier DBLP conf/vlsid/DevganR95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1995.512114 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Efficient simulation of interconnect and mixed analog-digital circuits in ACES. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anirudh_Devgan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ronald_A._Rohrer>
swrc:pages 229-233 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/DevganR95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/DevganR95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1995.html#DevganR95>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1995.512114>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject circuit analysis computing; mixed analogue-digital integrated circuits; analogue integrated circuits; integrated circuit interconnections; timing; transient analysis; ACES; adaptively controlled explicit simulation; timing simulation; mixed analog-digital circuits; analog circuit simulation; interconnect circuit simulation; AWE macromodels; nonlinear terminations; variable accuracy device models; circuit topology constraints removal; transient simulation (xsd:string)
dc:title Efficient simulation of interconnect and mixed analog-digital circuits in ACES. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document