[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/DuttaBGK10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Eric_A._M._Klumperink>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ramen_Dutta>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tarun_Kanti_Bhattacharyya>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiang_Gao_0002>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FVLSI.Design.2010.78>
foaf:homepage <https://doi.org/10.1109/VLSI.Design.2010.78>
dc:identifier DBLP conf/vlsid/DuttaBGK10 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FVLSI.Design.2010.78 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Eric_A._M._Klumperink>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ramen_Dutta>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tarun_Kanti_Bhattacharyya>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiang_Gao_0002>
swrc:pages 152-157 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/DuttaBGK10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/DuttaBGK10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#DuttaBGK10>
rdfs:seeAlso <https://doi.org/10.1109/VLSI.Design.2010.78>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject tapering factor, stage ratio, CMOS inverter, mismatch jitter, multiphase clock, low power, figure of merit (xsd:string)
dc:title Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document