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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/FernandezS96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/G._Enrique_Fernandez>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/R._Sridhar>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FICVD.1996.489628>
foaf:homepage <https://doi.org/10.1109/ICVD.1996.489628>
dc:identifier DBLP conf/vlsid/FernandezS96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FICVD.1996.489628 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Dual rail static CMOS architecture for wave pipelining. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/G._Enrique_Fernandez>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/R._Sridhar>
swrc:pages 335-336 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/vlsid/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/FernandezS96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/FernandezS96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid1996.html#FernandezS96>
rdfs:seeAlso <https://doi.org/10.1109/ICVD.1996.489628>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:subject CMOS logic circuits; pipeline processing; capacitance; delays; combinational circuits; timing; dual rail static CMOS architecture; wave pipelining; digital systems; throughput; gate capacitance; storage elements; delay variations; DRSCMOS; multi-functional basic building blocks; power consumption; combinational logic block (xsd:string)
dc:title Dual rail static CMOS architecture for wave pipelining. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document